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This paper presents a new method for fitting a convex piecewise-linear function to a given set of data, which can serve as an empirical modeling framework for circuit optimization via geometric programming. The method iteratively solves a series of linear optimization problems to minimize the fitting error. To reduce the fitting error in each iteration, an extra plane is added in the region where the largest error occurs. For verification, we apply the method to create transistor-level models in 90-nm complementary metal-oxide-semiconductor technology. Numerical results indicate that the proposed method can generate process-dependent transistor-level models with reasonable modeling accuracy.