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Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500

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3 Author(s)
Po-Lin Chen ; Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan ; Yu-Chieh Huang ; Tsin-Yuan Chang

The rapid advance of semiconductor technology exposes multifrequency designs to severe reliability loss due to incomplete at-speed testing, which is induced by ignorance of timing-related defects between clocks. However, the reduced testability caused by core-based design strategy also aggravates the difficulty in applying on-chip at-speed testing. Although previous works were able to successfully increase the quality of the at-speed testing, the diversity of on-chip clock control schemes from different components may complicate the test integration, increasing the test costs. Therefore, to accelerate the time-to-market and the time-to-volume, the development of a plug-and-play at-speed testing based on a well-defined test interface has become increasingly urgent. In this paper, a fast test integration approach for multi-clock-domain at-speed testing based on IEEE Standard 1500 is proposed. The proposed framework has been successfully integrated into an IEEE 1500-wrapped ultrawide-band design and a simple SoC design. Experiment results also confirm the feasibility of the proposed approach.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:29 ,  Issue: 11 )