Skip to Main Content
A fourth-order continuous-time (CT) Delta-Sigma modulator with 1.5-bit quantizer is presented in this paper. This design is targeted for audio applications that demand high resolution, low supply voltage, and low power consumption. The input-feedforward topology, with optimized coefficients, is utilized to reduce internal signal swings as well as the power consumption. A 1.5-bit quantizer with simple dynamic element matching (DEM) is used to improve resolution and stability. A novel feedforward and summation structure is applied in the 1.5-bit modulator to reduce the power consumption and the chip area, and to simplify the circuit. The modulator, designed in a 0.13-μm CMOS technology, achieves 100.5-dB peak SQNR (Signal-to-Quantization Noise Ratio), and 97.5-dB peak SQNDR (Signal-to-Quantization Noise-and-Distortion Ratio) over a 20-kHz signal bandwidth with a 2.56-MHz clock. The power consumption of the modulator is 42.6 μW under a 1-V supply, and the chip core area is 0.13 mm2.
Date of Conference: 22-24 Sept. 2010