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In order to reduce the design difficulties, the input sample-and-hold amplifier (SHA) is often removed in the nested background calibration of the CMOS pipelined analog-to-digital converters (ADC). The system uses a dual-channel LMS adaptive digital background calibration algorithm, and the reference ADC was calibrated in the foreground. Without the input SHA, the sampling-time error between the two channels is inevitable, requiring a new timing compensation block to be added to the digital background calibration algorithm. Simulations show that with the proposed method, the timing error is greatly reduced, and the tradeoffs between accuracy and power dissipation are relaxed.