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Full adder designed with MOSFET and single-electron transistor hybrid circuit

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3 Author(s)
Bingcai Sui ; Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China ; Liang Fang ; Yaqing Chi

It is generally accepted that, sooner or later, MOS-based circuits cannot be reduced further in (feature) size due to fundamental physical restrictions. Recently, many logic gates based on SET have emerged, representative SET/CMOS hybrid logic circuits are developed to avoid the disadvantage. The characteristics of SET are used to reduce the number of conventional devices. The tunable Coulomb oscillation characteristics are analyzed. As a trick, the cell with only one input port is analyzed to generate needed waveforms. Based on the cell, the Sum and Carry circuits are simply obtained. Simulation result shows that hybrid MOSFET/SET full adder can work normally at room temperature. One-bit full adder reduces much less area compared with complementary CMOS full adder, and not reduces the high performance. It is very useful for the logic and architecture design based on SET transistors.

Published in:

Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in

Date of Conference:

22-24 Sept. 2010