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Multi-step capacitor-splitting SAR ADC

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3 Author(s)
Lin, J. ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA ; Yu, W. ; Temes, G.C.

A new architecture is proposed which reduces the power consumption and capacitor area in successive approximation register (SAR) analogue-to-digital converters (ADCs). Two identical capacitor-splitting capacitor arrays are used in a two-step process for quantisation, and this significantly reduces the switching power and capacitor area.

Published in:

Electronics Letters  (Volume:46 ,  Issue: 21 )