By Topic

Multi-step capacitor-splitting SAR ADC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
J. Lin ; School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331, USA ; W. Yu ; G. C. Temes

A new architecture is proposed which reduces the power consumption and capacitor area in successive approximation register (SAR) analogue-to-digital converters (ADCs). Two identical capacitor-splitting capacitor arrays are used in a two-step process for quantisation, and this significantly reduces the switching power and capacitor area.

Published in:

Electronics Letters  (Volume:46 ,  Issue: 21 )