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A simulation study of lithography induced layout variations in 6-T SRAM cells is presented. Lithography simulations of a complete 6-T SRAM cell layout, including active n+/p+ regions layer and poly-gate layer were performed. The smallest feature size was assumed to be 45 nm. 76 positions of the projector focus were simulated for each layer in total. TCAD simulations of 32nm single gate FD SOI MOSFETs were performed to calculate the electrical behavior. SPICE parameters were extracted from reference results obtained by TCAD simulations. More than 5000 variations of the the static and dynamic SRAM cell performance in dependence on lithography induced variations of the physical transistor width and the physical gate length were simulated.