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The main focus of this paper is the implementation of mixed-signal peak current mode control in low-power dc-dc converters for portable applications. A DAC is used to link the digital voltage loop compensator to the analog peak current mode loop. Conventional DAC architectures, such as flash or ΔΣ are not suitable due to excessive power consumption and limited bandwidth of the reconstruction filter, respectively. The charge-pump based DAC (CP-DAC) used in this work has relatively poor linearity compared to more expensive DAC topologies; however, this can be tolerated since the linearity has a minor effect on the converter dynamics as long as the limit-cycle conditions are met. The CP-DAC has a guaranteed monotonic behavior from the digital current command to the peak inductor current, which is essential for maintaining stability. A buck converter IC, which was fabricated in a 0.18 μm CMOS process with 5 V compatible transistors, achieves a response time of 4 μs at fs=3 MHz and Vout=1 V, for a 200 mA load-step. The active area of the controller is only 0.077 mm2, and the total controller current-draw, which is heavily dominated by the on-chip senseFET current-sensor, is below 250 μA for a load current of Iout=50 mA.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:58 , Issue: 1 )
Date of Publication: Jan. 2011