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Nonlinearities in the time-to-digital converter (TDC) are a significant source of fractional spurs in a divider-less fractional-N ADPLL. Using an abstract model for the TDC, this paper presents a dithering method which is mathematically shown to suppress fractional tones, in conjunction with a feedforward dither cancellation technique which suppresses dither-induced phase noise. A mostly-digital calibration algorithm is also presented which ensures consistent phase noise cancellation across PVT conditions. The aforementioned techniques are implemented in a 65 nm digital CMOS prototype running at 3.5 GHz from a 35 MHz reference. The ADPLL demonstrates - 101 dBc/Hz in-band phase noise at a bandwidth of 3.4 MHz, - 58 dBc worst fractional spurious performance across the entire fractional range, and consumes 8.7 mW from a 1.2 V supply.