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A Power Efficient 12-bit and 25-MS/s Pipelined ADC for the ILC/Ecal Integrated Readout

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3 Author(s)
Fatah Rarbi ; PSI Electronics company, LPSC Laboratory ; Daniel Dzahini ; Laurent Gallin-Martel

The design of full integrated electronics readout for the future ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate the very front-end stages with an analog to digital converter. We present here a 12 bit 25 MHz analog to digital converter using a pipelined architecture. It is composed of ten 1.5 bit sub-ADCs along with a final 2 bit flash converter. A CMOS 0.35 μm process is used. The dynamic range is 2 V over a 3.3 V power supply and the total power dissipation is 37 mW. The analog part of the converter can be switched to a standby mode in only a couple of μs. This power management helps to reduce the DC power dissipation by three orders of magnitude. Therefore by switching the DC bias following the beam cycle time (1% of duty cycle), an average power consumption of only 0.2 μW is measured. The converter prototype occupies an active die area of 1.7 mm *0.6 mm.

Published in:

IEEE Transactions on Nuclear Science  (Volume:57 ,  Issue: 5 )