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The use of data dependence graphs in the design of bit-level systolic arrays

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3 Author(s)
McCanny, J.V. ; Dept. of Electr. & Electron. Eng., Queen''s Univ., Belfast, UK ; McWhirter, J.G. ; Sun-Yuan Kung

The use of bit-level systolic array circuits as building blocks in the construction of larger word-level systolic systems is investigated. It is shown that the overall structure and detailed timing of such systems may be derived quite simply using the dependence graph and cut-set procedure developed by S.Y. Kung (1988). This provides an attractive and intuitive approach to the bit-level design of many VLSI signal processing components. The technique can be applied to ripple-through and partly pipelined circuits as well as fully systolic designs. It therefore provides a means of examining the relative tradeoff between levels of pipelining, chip area, power consumption, and throughput rate within a given VLSI design

Published in:

Acoustics, Speech and Signal Processing, IEEE Transactions on  (Volume:38 ,  Issue: 5 )

Date of Publication:

May 1990

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