Referenced Items are not available for this document.
In this work, we introduce a true-single-phase-clock (TSPC) divider synthesis technique that is based on the general TSPC logic family. According to this unified technique, various types of TSPC dividers are compared in terms of the speed-power trade-off. The newly proposed RE-2 type has shown better balance between speed and power performance than other types. The measurement results of a prototype design in a 65 nm LP CMOS technology show that the maximal input frequencies can be 19 GHz and 16 GHz for a divide-by-2 divider and a divide-by-2/3 prescaler respectively, and the power consumption is less than 0.5 mW.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:45
,
Issue:
11
)
Date of Publication: Nov. 2010
- Page(s):
- 2457 - 2465
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 11596930
- Digital Object Identifier :
- 10.1109/JSSC.2010.2074290
- Product Type:
- Journals & Magazines
- Date of Publication :
- 14 October 2010
- Date of Current Version :
- 21 October 2010
- Issue Date :
- Nov. 2010
- Sponsored by :
- IEEE Solid-State Circuits Society
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