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Exploring NoC-Based MPSoC Design Space with Power Estimation Models

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5 Author(s)
Ost, L. ; Lab. of Comput. Sci., Robot. & Micro Electron. of Montpellier (LIRMM), Univ. of Montpellier, Montpellier, France ; Guindani, G. ; Moraes, F. ; Indrusiak, L.S.
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This model-based methodology and supporting toolset lets designers estimate application-specific network-on-chip (NoC) power dissipation at early stages of the design flow. An actor-oriented simulation framework captures the NoC's dynamic behavior and feeds its parameters to a rate-based power estimation model. Integrating this model into the proposed design flow enables the analysis of different design parameters and the identification of the most power-efficient application platform mappings.

Published in:

Design & Test of Computers, IEEE  (Volume:28 ,  Issue: 2 )