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Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture

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3 Author(s)
Kun Fang ; Dept. of ECE, Univ. of Illinois at Chicago, Chicago, IL, USA ; Hongzhong Zheng ; Zhichun Zhu

Memory power consumption has become a big concern in server platforms. A recently proposed mini-rank architecture reduces the memory power consumption by breaking each DRAM rank into multiple narrow mini-ranks and activating fewer devices for each request. However, its fixed and uniform configuration may degrade performance significantly or lose power saving opportunities on some workloads. We propose a heterogeneous mini-rank design that sets the near-optimal configuration for each workload based on its memory access behavior and its memory bandwidth requirement. Compared with the original, homogeneous mini-rank design, the heterogeneous mini-rank design can balance between the performance and power saving and avoid large performance loss. For instance, for multiprogramming workloads with SPEC2000 application running on a quad-core system with two-channel DDR3-1066 memory, on average, the heterogeneous mini-rank can reduce the memory power by 53.1% (up to 60.8%) with the performance loss of 4.6% (up to 11.1%), compared with a conventional memory system. In comparison, the ×32 homogeneous mini-rank can only save memory power by up to 29.8%; and the ×8 homogeneous mini-rank will cause performance loss by up to 22.8%. Compared with ×16 homogeneous mini-rank configuration, it can further reduce the EDP (energy-delay product) by up to 15.5% (10.0% on average).

Published in:

2010 39th International Conference on Parallel Processing

Date of Conference:

13-16 Sept. 2010