Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding

There is an increasing demand for converged solution for multi-standard radio processors to support existing and future standards. In this work, heterogeneous multi-processor platform is proposed for multi standard wireless communication system which is programmable and scalable in adapting to future standards. Channel decoding algorithms form important constituent of wireless communication system because of their computational complexity. A programmable radio processor is proposed for channel decoding with application specific instruction accelerators. Viterbi and Turbo channel decoding algorithms are analyzed for computational parallelism in the algorithms and for hardware reusability across the algorithms. Application specific instruction accelerator is designed by exploiting similar characteristics and computational parallelism across the algorithms. The analysis shows that the throughput of 54Mbps for UWB Viterbi Decoder and 12 Mbps for UMTS Turbo Decoder at 91.7MHz can be achieved using the proposed design.