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In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

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3 Author(s)
Mehta, Nandish ; Department of ECE, Indian Institute of Science, Bangalore, India 560012 ; Naik, Gururaj ; Amrutur, B.

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Published in:

Low-Power Electronics and Design (ISLPED), 2010 ACM/IEEE International Symposium on

Date of Conference:

18-20 Aug. 2010

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