By Topic

Reducing instruction TLB's leakage power consumption for embedded processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Zhao Lei ; Dept. of Comput. Sci. & Inf., Keio Univ., Yokohama, Japan ; Hui Xu ; Ikebuchi, D. ; Amano, H.
more authors

This paper presents a leakage efficient instruction TLB (Translation Lookaside Buffer) design for embedded processors. The key observation is that when programs enter a physical page following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage structure which stores the recent address-translation information, the TLB access frequency can be drastically decreased and the instruction TLB can be turned into the low leakage mode with the dual voltage supply technique. Based on such a design philosophy, three different implementation policies are proposed. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation.

Published in:

Green Computing Conference, 2010 International

Date of Conference:

15-18 Aug. 2010