Cart (Loading....) | Create Account
Close category search window

Efficient design and fabrication of CMOS active pixel sensors through modeling and simulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)

Design and optimization of backside-thinned CMOS active pixel sensors (APS) using modeling and simulation is presented. For the efficient design and the further improvement of our backside-thinned CMOS imagers, different models were developed and TCAD simulating tools were used. The imagers have been successfully designed, fabricated and tested and proved to possess excellent imaging properties. This short abstract paper presents a summary of the models and simulations covering two critical design and processing issues, namely the epilayer (EPI) structure and the pixel isolating trench formation process as well as their influence on the electrical inter-pixel crosstalk.

Published in:

Numerical Simulation of Optoelectronic Devices (NUSOD), 2010 10th International Conference on

Date of Conference:

6-9 Sept. 2010

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.