By Topic

Matrix computation on Connex Parallel Architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Calfa, A.-M. ; Fac. of Electron. & Telecommun., Politech. Univ. of Bucharest, Bucharest, Romania ; Stefan, G.

The parallel Connex Architecture has specific features imposed in order to improve GIPS/Watt and GIPS/mm2. It is designed for embedded computation in systems on chip design. Its validation supposes exploring by turn different application domains to see how the specific architectural and design assumptions affected the actual performance. In this paper the domain of matrix computation is preliminary investigated.

Published in:

Signals and Electronic Systems (ICSES), 2010 International Conference on

Date of Conference:

7-10 Sept. 2010