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Direct Tunnelling Gate Leakage Variability in Nano-CMOS Transistors

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3 Author(s)
Markov, S. ; Dept. of Electron. & Electr. Eng., Univ. of Glasgow, Glasgow, UK ; Roy, S. ; Asenov, A.

A comprehensive simulation methodology for the systematic study of gate leakage variability in realistic nanoscale bulk CMOS transistors, on a statistical scale, is presented for the first time. This is based on the Glasgow “atomistic” 3-D drift-diffusion device simulator with density-gradient quantum corrections, which is capable of modeling various sources of stochastic variability, including random dopant fluctuations (RDFs) and oxide thickness fluctuations (OTFs). The capabilities of the simulator are extended to model direct tunnelling of electrons through the gate dielectric by means of an improved Wentzel-Kramer-Brillouin approximation with one model parameter only. The methodology is applied for the detailed study of the gate leakage variability arising from RDFs and OTFs in a 25-nm square-gate n-channel metal-oxide-semiconductor field-effect transistor with conventional architecture. The origins of gate leakage variability and gate current increase due to RDFs and OTFs individually, and in combination, are analyzed for bias conditions that are relevant to static power dissipation in digital CMOS circuits.

Published in:

Electron Devices, IEEE Transactions on  (Volume:57 ,  Issue: 11 )

Date of Publication:

Nov. 2010

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