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Mechanisms of Noise Degradation in Low Power 65 nm CMOS Transistors Exposed to Ionizing Radiation

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5 Author(s)
Valerio Re ; Dipartimento di Ingegneria Industriale, Universit? di Bergamo, Dalmine, Italy ; Luigi Gaioni ; Massimo Manghisoni ; Lodovico Ratti
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Experimental data provide insight into the mechanisms governing the impact of gate and lateral isolation dielectrics and of scaling-related technological advances on noise and its sensitivity to total ionizing dose effects in Low Power 65 nm CMOS devices. The behavior of the 1/f noise term is correlated with the effects on the drain current that irradiation brings along by turning on lateral parasitic transistors. A comparison with data from previous CMOS generations is carried out to assess the impact of process features on radiation-induced degradation effects.

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IEEE Transactions on Nuclear Science  (Volume:57 ,  Issue: 6 )