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Scheduling Algorithms for Minimizing Tardiness of Orders at the Burn-in Workstation in a Semiconductor Manufacturing System

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4 Author(s)
Yeong-Dae Kim ; Department of Industrial Engineering, Korea Advanced Institute of Science and Technology, Yusong-gu, Daejeon, Korea ; Jae-Hun Kang ; Gyeong-Eun Lee ; Seung-Kil Lim

In this paper, we consider a scheduling problem in a semiconductor test facility. We focus on the burn-in workstation and its corresponding loading/unloading workstation, which may be considered bottleneck workstations in the test facility. In the burn-in workstation, there are parallel identical batch-processing machines, called chambers, while there are unrelated parallel machines in the loading/unloading workstation. We present heuristic algorithms for the scheduling problem at the burn-in workstation as well as the loading/unloading workstation with the objective of minimizing total tardiness of orders. For evaluation of performance of the algorithms, a series of computational experiments are performed on a number of problem instances, and results show that the suggested heuristic algorithms outperform existing scheduling rules that are currently used in a real system.

Published in:

IEEE Transactions on Semiconductor Manufacturing  (Volume:24 ,  Issue: 1 )