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Design and fabrication of a mems capacitive accelerometer based on double-device-layers SOI wafer

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6 Author(s)
Qifang Hu ; Nat. Key Lab. of Sci. & Technol. on Micro/Nano Fabrication, Peking Univ., Beijing, China ; Chengchen Gao ; Yilong Hao ; Dacheng Zhang
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This paper presents a capacitive MEMS accelerometer with highly symmetric sandwich structure (Glass-Si-Glass). In order to get highly symmetric beam-mass structure (silicon middle-layer), a double-device-layer SOI (D-SOI) wafer, which has identical buried oxides (BOX) and device layers on both sides of a thick handle layer was adopted in fabrication. The fabrication process produced proof mass with though wafer thickness (1mm) to increase the sensitivity of the accelerometer. Two layers of single crystal silicon beams with highly uniform dimension suspended the proof mass from both sides symmetrically. The highly symmetric beam-mass structure reduced the cross axis sensitivity and rotational influences of the microaccelerometer dramatically. Two glass cap wafers with capacitance electrodes were anodic bonded with middle-layer wafer to form the capacitances. Initial capacitances designed to be 80pF were measured in the range of 75.03~86.94pF. The amplitude of capacitances variation up to 55pF/±1g was measured.

Published in:

Nano/Micro Engineered and Molecular Systems (NEMS), 2010 5th IEEE International Conference on

Date of Conference:

20-23 Jan. 2010

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