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In this paper, a novel compact structure design for minimizing the chip area cost is proposed. The improvement in sensitivity and temperature drift for silicon piezoresistive force sensor is evaluated. The sensitivity improvement can be obtained by adding a long flexible cantilever, and locating stress-sensitive element at a high stressed area close to the bottom surface of the lower cantilever. An ultra-thin Si film beneath interconnect layer can be obtained by a STI (shallow trench isolation) protection etch process. The simulation results show relative saturation drain current change of MOSFETs can achieve up to about 0.87% at 10g acceleration and the temperature fluctuations only 0.918 and 0.972°C when it is exposed to -45 and 150°C atmospheric temperatures, respectively.