Skip to Main Content
In deep sub-micrometer (DSM) regime the on-chip interconnects delay is significantly more dominating than the gate delay. Several approaches have been proposed to capture the interconnect delay accurately and efficiently. Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans-impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions In this paper we have proposed an accurate and efficient model to compute the delay and slew metric of on-chip interconnect of high speed CMOS VLSI designs. We used the PERI (Probability distribution function Extension for Ramp Inputs) technique to the Weibull distribution that extends delay and slew metrics for step inputs to the more general and realistic non-step inputs. The accuracy of our model is justified with the results compared with that of SPICE simulations.