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There is an increasing need for configurable quasi-cyclic low-density parity-check (QC-LDPC) decoders that can support a family of structurally compatible codes instead of a single code. The key component in a configurable QC-LDPC decoder is a programmable circular-shift network that supports cyclic shifts of any size up to a predefined maximum submatrix size. This paper presents a QC-LDPC shift network (QSN), which has two key advantages over state-of-the-art solutions in recent literature. First, the QSN reduces the number of stages in the critical path, which improves the clock frequency and makes it scalable, particularly in a field-programmable gate array (FPGA)-based implementation where an interconnect delay is dominant. Second, the QSN's control logic is simple to generate and occupies a significantly smaller area. The QSNs for a variety of codes suitable for emerging applications are implemented, targeting both a 180-nm Taiwan Semiconductor Manufacturing Company Ltd. complimentary metal-oxide-semiconductor library and a Xilinx Virtex 4 FPGA. The proposed implementation is shown to be 2.1 times faster than the best known implementation in literature and requires almost eight times less control area. Furthermore, this paper presents analytical models of the critical-path and datapath complexity for arbitrary-sized submatrices and proves that the QSN indeed generates all the output combinations required for implementing reconfigurable QC-LDPC decoders.