By Topic

An ultra low-power CMOS frequency synthesizer for low data-rate sub-GHz applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ippolito, C.M. ; Dipt. di Ing. Elettr. Elettron. e dei Sist., Univ. di Catania, Catania, Italy ; Italia, A. ; Palmisano, G.

An ultra low-power frequency synthesizer for sub-GHz applications was designed and implemented in a 90-nm CMOS technology. Based on an integer-N phase-locked loop architecture, the frequency synthesizer covers the 0.3-0.95 GHz band almost continuously with 150-kHz channel steps. Multi-band operation is achieved thanks to a wideband low-power LC VCO, which makes use of shunt-connected switched-coupled inductors. Power consumption has been minimized by adopting true single-phase clocked logic cells for the first stages of the programmable divider. The frequency synthesizer achieves a phase noise of -96 dBc/Hz at 150-kHz offset frequency. The measured settling time is around 350 μS and the reference spurs are lower than -52 dBc. The circuit power consumption is only 1.8 mW from a 1.2-V supply.

Published in:

Ph.D. Research in Microelectronics and Electronics (PRIME), 2010 Conference on

Date of Conference:

18-21 July 2010