A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors

An 11-bit 160-MS/s four-channel time-interleaved double-sampled pipelined ADC implemented in a 0.35-
$\mu{\hbox {m}}$
CMOS process is described. Digital calibration is used to correct mismatch errors between channels as well as the memory errors that arise from the use of double sampling. The signal-to-noise-and-distortion ratio is improved from 45 to 62 dB after calibration with an 8.7-MHz input. The spurious-free dynamic range is increased from 47 dB to 79 dB.