Referenced Items are not available for this document.
An 11-bit 160-MS/s four-channel time-interleaved double-sampled pipelined ADC implemented in a 0.35-μm CMOS process is described. Digital calibration is used to correct mismatch errors between channels as well as the memory errors that arise from the use of double sampling. The signal-to-noise-and-distortion ratio is improved from 45 to 62 dB after calibration with an 8.7-MHz input. The spurious-free dynamic range is increased from 47 dB to 79 dB.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:45
,
Issue:
10
)
Date of Publication: Oct. 2010
- Page(s):
- 2091 - 2103
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 11535252
- Digital Object Identifier :
- 10.1109/JSSC.2010.2061630
- Date of Current Version :
- 23 September 2010
- Issue Date :
- Oct. 2010
- Sponsored by :
- IEEE Solid-State Circuits Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
