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In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase memory cells are presented for achieving high program inhibition with lower program disturbance in sub-40 nm MLC NAND flash and beyond. Simple two-step dynamic Vpass control technique is used and over 40% program failure reduction after 30 k P/E cycling is achieved in the proposed scheme, compared to conventional method. A major pattern dependency of program disturbance in MLC NAND flash is also described in this paper. In order to achieve high immunity for the data pattern dependency in program disturbance, optimizing erase Vth and its distribution using ISPP-after-erase with a precise negative Vth sensing scheme are proposed. The proposed schemes are demonstrated using 42 nm MLC NAND flash test chip and about 2 times better Vpass window margin is obtained compared to conventional scheme.
Date of Publication: Oct. 2010