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The advent of wideband systems, e.g., software defined radios, cognitive radios and UWB technology, motivates research for new transceiver architectures and circuit topologies to arrive at compact and low power solutions. Reference frequency generation in wideband CMOS receivers is usually power and area hungry. In this paper a wide band quadrature demodulator, based on mixers reconfigurable between fundamental and sub-harmonic operation modes is presented. The technique allows covering an RF bandwidth three times larger than the frequency covered by the synthesizer. Multiple local oscillator phases are required for the proposed architecture. For low phase noise and fast settling time, they are generated by means of a multi-stage injection locked ring oscillator. This solution proves very accurate and power efficient and may find applications in other communication systems requiring multiple phase references. A demodulator test chip tailored to WiMedia UWB groups 1, 3, 4 (3.1-9.5 GHz), and comprising mixers and frequency synthesizer, has been realized in a 65 nm CMOS technology. Experimental results show 10 dB of conversion gain with 2.3 nV/sqrt(Hz) equivalent input noise voltage spectral density. IIP2 and IIP3, with interferers in the GSM and WLAN bands, are 40 dBm and 11 dBm respectively. The synthesizer displays maximum spurs level of -43 dBc, a state of the art phase noise of -128 dBc/Hz@10 MHz offset and a settling time of less than 6 ns with 43 m W only.