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A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations

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1 Author(s)
Byung-Do Yang ; Sch. of Electr. & Comput. Eng., Chungbuk Nat. Univ., Cheongju, South Korea

This paper proposes a low-power SRAM using bit-line charge-recycling for read and write operations. The charge-recycling SRAM (CR-SRAM) reduces the read and write powers by recycling the charge in bit lines. When N bit lines recycle their charges, the swing voltage and power of bit lines are reduced to 1/N and 1/N2, respectively. The CR-SRAM utilizes hierarchical bit-line architecture to perform the charge-recycling without static noise margin degradation in memory cells. In the simulation, the CR-SRAM saves 17% read power and 84% write power compared with the conventional SRAM. A CR-SRAM chip with 4 K × 8 bits is implemented in a 0.13-μm CMOS process. It consumes 0.128-mW read power and 0.135-mW write power at fCLK = 100 MHz and VDD = 1.2 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 10 )

Date of Publication:

Oct. 2010

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