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An asynchronous low latency ordered arbiter for network on chips

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4 Author(s)
Yu Liu ; Inst. of Microelectron., Xidian Univ., Xi''an, China ; Xuguang Guan ; Yang Yang ; Yintang Yang

To improve two shortcomings of traditional arbiters, large arbitration latency and limited correctness, this paper proposes a low latency ordered arbiter. Through arranging input requests arbitrated at the same stage, correctness of the arbiter can be guaranteed, also the strict first come first service (FCFS) can be realized, so as to improve the quality of service (QoS) of the on chip router. The proposed ordered arbiter is implemented based on BPTM 65 nm CMOS technology. Results demonstrate this ordered arbiter has significant improvement on arbitration delay, and the area overheads are nearly the same as traditional ones. The proposed ordered arbiter can apply to network on chips which have QoS demand and high speed applications.

Published in:

Natural Computation (ICNC), 2010 Sixth International Conference on  (Volume:2 )

Date of Conference:

10-12 Aug. 2010