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Real-time software MPEG-1 video decoder design for low-cost, low-power applications

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5 Author(s)
Nadehara, K. ; Inf. Technol. Res. Labs., NEC Corp., Kawasaki, Japan ; Stolberg, H.J. ; Ikekawa, M. ; Murata, E.
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This paper presents a real-time MPEC-1 video decoder implemented in software on a DSP-enhanced, 160-mW, 100-MHz, 32-bit microprocessor. The processor's DSP-oriented instructions improves the performance of generic DSP operations such as the inverse discrete cosine transform, while fast software algorithms that perform parallel operation on packed-pixel data are developed for processes unique to video decoding such as motion compensation. Furthermore, to reduce the clock count as well as the instruction count, load/store scheduling and cache miss reduction are performed. In total, the processor can achieve 30 frames/sec MPEC-1 video decoding at a cost and power dissipation (160 mW) comparable to dedicated LSIs

Published in:

VLSI Signal Processing, IX, 1996., [Workshop on]

Date of Conference:

30 Oct-1 Nov 1996

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