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A scalable architecture for 2-D discrete wavelet transform

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2 Author(s)
Limqueco, J.C. ; Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA ; Bayoumi, M.A.

We propose an efficient and simple systolic-like architecture for VLSI implementation of a 2-D discrete wavelet transform (DWT). The “approximation” and “detailed” components of a signal are computed simultaneously in the first octave and alternately in the other octave(s). Each processing element has its own local memory for storing intermediate data and minimum routing requirement limited only to its neighbors. The proposed architecture uses the same clock frequency for every octave level and has a 100% utilization for j=2 architecture, and N2+N period cycle. The architecture is scalable for different filter lengths (divisible by 2) and different octave levels

Published in:

VLSI Signal Processing, IX, 1996., [Workshop on]

Date of Conference:

30 Oct-1 Nov 1996