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SHARP: efficient loop scheduling with data hazard reduction on multiple pipeline DSP systems

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4 Author(s)
Tongsima, S. ; Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA ; Chantrapornchai, C. ; Sha, E. ; Passos, N.L.

Computation intensive DSP applications usually require a parallel/pipelined processor in order to achieve specific timing requirements. Data hazards are a major obstacle against the high performance of pipelined systems. This paper presents a novel efficient loop scheduling algorithm that reduces data hazards for those DSP applications. Such an algorithm has been embedded in a tool, called SHARP, which schedules a pipelined data flow graph to multiple pipelined units, while hiding the underlying data hazards and minimizing the execution time. This paper reports significant improvement for some well-known benchmarks, showing the efficiency of the scheduling algorithm and the flexibility of the simulation tool

Published in:

VLSI Signal Processing, IX, 1996., [Workshop on]

Date of Conference:

30 Oct-1 Nov 1996