By Topic

Parallel and pipelined architecture designs for distributed arithmetic-based recursive digital filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Yin-Tsung Hwang ; Dept. of Electron. Eng, Nat. Yunlin Inst. of Technol., Taiwan ; Ching-Long Su

This paper presents a distributed arithmetic based design scheme for recursive DSP systems requiring high speed computing. The proposed scheme features a bit-serial word-parallel approach and is found more efficient than the conventional bit-parallel word-serial scheme. We apply this scheme to design an ARMA filter and yield an initiation interval as small as the delay of processing only one output bit. We also incorporate the look-ahead transform and the block processing techniques in the proposed DA scheme for further speed improvement. Finally, we propose a signed digit DA scheme to solve the performance degradation problem due to the effect of data word length truncation in fixed point number computing systems

Published in:

VLSI Signal Processing, IX, 1996., [Workshop on]

Date of Conference:

30 Oct-1 Nov 1996