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A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits

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3 Author(s)
P. A. Beerel ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; K. Y. Yun ; Wei-Chun Chou

Presents a covering technique for optimizing the average-case delay of asynchronous burst-mode control circuits during technology mapping. The specification and the NAND-decomposed unmapped network of these circuits are first preprocessed using stochastic techniques to determine the relative frequency of occurrence of each state transition and the corresponding sensitized paths through the NAND-decomposed network. We minimize the sum of the implementation's cycle times of the state transitions, weighted by their relative frequencies, thereby optimizing for average-case performance. Our results demonstrate that a 10-15% improvement in performance con be achieved with run-times comparable to synchronous techniques

Published in:

Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European

Date of Conference:

16-20 Sep 1996