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As technology pushes deeper into the nanoscale, the difficulty in developing high-performance analog functions has driven an explosion in digitally intensive architectures to replace them. Commonalities among these new architectures include a paradigm shift toward temporal versus voltage encoding of analog signals, and the extensive use of digital calibration. In particular, recent developments in fractional-N all-digital phase-locked loops (ADPLLs) have proven them to be competitive with analog state of the art for narrowband applications, demonstrating excellent phase noise and achieving even traditionally difficult standards such as GSM. However, to achieve comparable high performance for wideband applications requires a reduction in fractional spurs. This paper provides a brief summary of ADPLL architectures, leading to a prototype synthesizer at 3 GHz which implements a spurious tone reduction technique. Along the way, an efficient simulation model to predict fractional spur amplitude and frequency in ADPLLs is presented. The 3 GHz prototype operates from a flexible reference frequency, between 25 MHz-100 MHz, has in-band phase noise of -101 dBc/Hz with a decade of loop bandwidth programmability, and in-band spurs below -45 dBc. The synthesizer occupies 0.4 mm2 in 65 nm digital CMOS and consumes less than 10 mW from a 1.2 V supply.