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Digital receiver frontends have emerged as a possible solution for the next-generation serial I/O receiver design in advanced CMOS technologies. The challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs. With a power budget of <; 20 mW/Gb/s, the feasibility of an ADC-based receiver is limited by the high-speed analog-to-digital converter (ADC) and complex digital processing in current fabrication technologies. In this paper, various designs and architectures for each component of an ADC-based receiver and their performance trade-offs are discussed. The design requirement of an ADC and digital processing can be relaxed with the aid of simple mixed-mode circuitry. More complex digital processing techniques are becoming feasible with the scaling of CMOS technology. However, the improvement from scaling is limited by the substantial leakage current, and the rate of improvement is slowing beyond 32 nm technology node.