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ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies

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4 Author(s)
Shuqing Cao ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Jung-Hoon Chun ; Beebe, S.G. ; Dutton, R.W.

Challenges of electrostatic discharge (ESD) protection in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O MOSFETs, interconnect, ESD protection and power clamp devices. Recent progress on ESD protection design for both high-speed digital I/O and radiofrequency (RF) circuits are presented. Topological trade-offs are compared. High speed circuit protection techniques such as the T-coil based ESD design are reviewed in detail. Package- and wafer-level charged device model (CDM) correlation issues are discussed. I/O, ESD devices, and metal interconnect effects are examined using very fast transmission line pulses (VF-TLP) and TLP.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:57 ,  Issue: 9 )