Referenced Items are not available for this document.
This paper presents a new concept for accurately modeling the timing behavior of VLSI interconnections using frequency domain methods and taking into consideration distributed parasitics as well as lumped elements and contact holes. A piecewise linear signal representation is used to catch the waveform dependencies of submicron structures. The models are applied in an analysis tool for clock trees and in a concept for accurate post-layout timing simulation
Published in:
Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European
Date of Conference: 16-20 Sep 1996
- Page(s):
- 72 - 77
- Meeting Date :
- 16 Sep 1996-20 Sep 1996
- Print ISBN:
- 0-8186-7573-X
- INSPEC Accession Number:
- 5412401
- Conference Location :
- Geneva
- Digital Object Identifier :
- 10.1109/EURDAC.1996.558186
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
