By Topic

Issues on the size and outline of killer defects and their influence on yield modeling

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hess, C. ; Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany ; Weiland, L.H.

Yield prediction models and critical area calculations based on on defects modeled as circular disks. But, the observation of real defects provides mostly irregular defect outlines. For this reason, we investigate the influence of real defect outlines on determining defect size distributions for yield prediction. To collect data on defects, checkerboard test structures were manufactured that enable a precise localization of defects inside large chip areas. Furthermore, we introduce a methodology to calculate a general defect size distribution that includes variety of real defect outlines. So, this realistic size distribution will be compared to defect size distributions based on known yield models to describe defect outlines

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996

Date of Conference:

12-14 Nov 1996