Referenced Items are not available for this document.
Wafer-level defect distributions and yield patterns are a significant source of information about the performance of a manufacturing line. Computer-based techniques are ideal for pattern analysis because they provide the ability to quickly perform systematic, repetitive analyses on large data sets. The development of algorithms for computer-based spatial pattern analysis are described and initial test results are presented. Integration of automated spatial pattern analysis into the manufacturing process is discussed
Published in:
Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996
Date of Conference: 12-14 Nov 1996
- Page(s):
- 409 - 415
- Meeting Date :
- 12 Nov 1996-14 Nov 1996
- ISSN :
- 1078-8743
- Print ISBN:
- 0-7803-3371-3
- INSPEC Accession Number:
- 5527075
- Conference Location :
- Cambridge, MA
- Digital Object Identifier :
- 10.1109/ASMC.1996.558099
- Product Type:
- Conference Publications
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