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Routers need to store temporarily a large number of packets in response to congestion. DRAM is typically needed to implement large packet buffers, but DRAM devices have worst-case random access latencies that are too slow to match the bandwidth requirements of high-performance routers. Existing DRAM-based architectures for supporting linespeed queue operations can be classified into three categories: prefetching-based, randomization-based, and reservation-based. They are all based on interleaving memory accesses across multiple parallel DRAM banks for achieving higher memory bandwidths, but they differ in their packet placement and memory operation scheduling mechanisms. In this paper, we present an efficient reservation-based packet buffer architecture based on the concept of blocks. The proposed block-based solution achieves an order of magnitude reduction in the total SRAM size. It is scalable to growing packet storage requirements in routers while matching increasing line rates.
Date of Conference: 13-16 June 2010