By Topic

RTL-TLM equivalence checking based on simulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Nicola Bombieri ; Dept. of Comput. Sci., Univ. Verona, Verona, Italy ; Franco Fummi ; Graziano Pravadelli

The always increasing complexity of digital systems is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at different abstraction levels above RTL. The bottom-up approach is often adopted in the design flow when already existing RTL IPs are abstracted to be reused into the TLM system. In this context, proving the equivalence between a model and its abstracted version is still an open problem. In fact, traditional equivalence definitions and formal equivalence checking methodologies presented in the literature cannot be applied due to the very different internal characteristics of the models. In this paper, we propose a methodology based on simulation which gives two important contributes. Firstly, it relies on a suite of tools to automate as much as possible the equivalence verification process. Then, a more accurate definition of the equivalence concept is proposed by giving two quality measures of stimuli automatically generated for checking the equivalence between the generated TLM and the RTL golden model.

Published in:

Design & Test Symposium (EWDTS), 2008 East-West

Date of Conference:

9-12 Oct. 2008