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Utilizing HDL simulation engines for accelerating design and test processes

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3 Author(s)
Najmeh Farajipour ; CAD Res. Group, Univ. of Tehran, Tehran, Iran ; S. Behdad Hosseini ; Zainalabedin Navabi

This paper introduces a complete test package in VHDL that makes it possible to simulate faults and generate test patterns for a component during its design process. Different approaches on test applications can be combined and then be applied to combinational, sequential and scan-based circuits in a fully configurable and convenient environment. To reveal the capabilities of VHDL in test configurations, we used two different approaches for fault simulation and evaluated them with random tests.

Published in:

Design & Test Symposium (EWDTS), 2008 East-West

Date of Conference:

9-12 Oct. 2008