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A 0.64 mm ^{2} Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

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3 Author(s)
Chih-Rung Chen ; Dept. of Comput. Sci., Nat. Tsing-Hua Univ., Hsinchu, Taiwan ; Wei-Su Wong ; Ching-Te Chiu

Face detection is widely used in portable consumer handheld devices aimed at low area, low power, and high performance applications. The boosted cascade algorithm is one of the fastest face detection algorithms in use, but its hardware implementation requires a huge amount of SRAM to store the input data, integral image, and classifiers. This paper proposes a novel cascade face detection architecture based on a reduced two-field feature extraction scheme for faster integral image calculation and feature extraction. This scheme reduces the required memory for storing integral images by 75%, and employs multiple register files instead of a single SRAM to speed up the integral image updating and feature extraction processes. The reduced integral images have only 5% of the features of original images. Although this approach requires more weak classifiers, the proposed parallel cascade detection architecture reduces the average detection time for one feature to 63% that of the original. A 0.64 mm2 15 mw (@390 fps) boosted cascade face detection is implemented under the UMC 90-nm CMOS technology. Experimental results show that this face detection system can achieve a high face detection rate in processing 160 × 120 grayscale images at a speed of 390 fps.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 11 )
Biometrics Compendium, IEEE