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Cycle time reduction program at ACL

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2 Author(s)
Boebel, F.G. ; Siemens SA, Corbeil-Essonnes, France ; Ruelle, O.

In this paper we focus on the results of the DRAM production cycle time team with special emphasis on: how does CT translate into productivity; what tools are needed for effective CT analysis including daily going rate (DGR) issues; how to find and how to fight the main CT detractors The results are compared with the real world execution at the SIEMENS/IBM Advanced CMOS line (ACL) in Essonnes-Corbeil

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996

Date of Conference:

12-14 Nov 1996