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Non-linearity and randomness in a semiconductor wafer fab

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1 Author(s)
S. S. Johal ; Analog Devices Inc., Wilmington, MA, USA

Conventional intuition of semiconductor wafer fab performance relies on assumptions of linear work flow and fixed (deterministic) behavior of the fab equipment's breakdown and capacity. This intuition is used to analyze fab capacity by using simple mathematical models in a “spreadsheet” fashion to obtain feasibility bounds on capacity (wafers out/unit time), cycle time (or lead time) and work-in-progress levels. However, assumptions of linearity and fixed behavior are not always valid, especially when strategic analysis needs to be done over long time horizons. This paper demonstrates the effects of such non-linearities and random (stochastic) behavior. This is done by modeling simple fab scenarios using advanced mathematical and discrete-event simulation tools. In particular, effects of a high degree of variance on equipment availability are investigated using serial representations of a manufacturing line. The impact of setup change-over times is also analyzed through random queuing scenarios in order to arrive at more accurate results of the line loading phenomenon. These results are then statistically analyzed to provide a contrast to conventional intuition

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996

Date of Conference:

12-14 Nov 1996